Design and implementation of an efficient CNN accelerator for low-cost FPGAs

This paper proposes a computation-array-centered dataflow, which adjusts the convolution with different kernel sizes to unified computing manner and reduces dimension of computation array from 2D 1D, so as maximize utilization elements offered by accelerator. Furthermore, single unit multiple data (SUMD) strategy is proposed effectively alleviate mismatch between quantized hardware resources fixed bit width on FPGA. As case study, an 8-bit MobileNetV2 model has been implemented low-cost ZYNQ XC7Z020 FPGA, whose FPS/DSP GOPS/DSP achieve upto 0.55 0.35 respectively.